Many electronic devices employ microprocessors or other digital circuits which require one or more clock signals for synchronization. A clock signal permits the precise timing of events in the microprocessor, for example. Typical microprocessors may be supervised or synchronized by a free-running oscillator, such as driven by a crystal, an LC-tuned circuit, or an external clock source. Clocking rates up to and beyond 40 MHz are common in personal computers. The parameters of a clock signal are typically specified for a microprocessor and may include minimum and maximum allowable clock frequencies, tolerances on the high and low voltage levels, maximum rise and fall times on the waveform edges, pulse-width tolerance if the waveform is not a square wave, and the timing relationship between clock phases if two-clock phase signals are needed. (See Electronics Engineers' Handbook, by Fink et al., p. 8-111, 1989.)
Unfortunately, high performance, microprocessor-based devices using leading edge, high speed circuits are particularly susceptible to generating and radiating electromagnetic interference (EMI). The spectral components of the EMI emissions typically have peak amplitudes at harmonics of the fundamental frequency of the clock circuit. Accordingly, many regulatory agencies, such as the FCC in the United States, have established testing procedures and maximum allowable emissions for such products. For example, the Commission Electrotechnique International (Comite International Special Des Perturbations Radioelectriques (C.I.S.P.R.)) has guidelines establishing measurement equipment and techniques for determining compliance with regulations. More particularly, for the frequency band of interest to clock circuits, the measured 6 dB bandwidth is a relatively wide 120 KHz.
In order to comply with such government limits on EMI emissions, costly suppression measures or extensive shielding may be required. Other approaches for reducing EMI include careful routing of signal traces on printed circuit boards to minimize loops and other potentially radiating structures. Unfortunately, such an approach often leads to more expensive multilayer circuit boards with internal ground planes. In addition, greater engineering effort must go into reducing EMI emissions. The difficulties caused by EMI emissions are made worse at higher processor and clock speeds.
In certain applications it is necessary to precisely synchronizes the period of one clock with that of another. Accordingly, precise control of the modulation of a clock signal can be significant. In this invention digital spread spectrum modulation circuits are preferably used. These circuits are synchronized by resetting a counter which controls the circuit. Spread spectrum clock implementations employing a voltage controlled oscillator but not digital control are disclosed in U.S Pat. No. 4,507,796 to Stumfall. Digital control circuits of some similarity, not for spread spectrum clock control, are disclosed in U.S. Pat. No. 3,764,933 to Fletcher et al, U.S. Pat. No. 3,962,653 to Basset, 4,943,786 to Cordwell et al, and 5,028,887 to Gilmore. Digital FM communication circuits of some similarity are disclosed in U.S. Pat. No. 5,272,454 to Ikai et al, 5,301,367 to Heinonen, and 5,329,253 to Ichihara.
A digital implementation mentioned beginning at page 19, line 21 in the foregoing parent application, but not shown in the drawing, is now prior art with respect to the filing date of this application. That has data digitally stored which is applied to an adder and accumulated. The output of the accumulator is one input to a phase detector of a phase locked loop, the other input being a divided feedback from the output of the voltage controlled oscillator of the phase locked loop. The output of that oscillator is divided and used as the spread spectrum clock signal.--No disclosed embodiment of this invention employs such an adder or accumulator.